This invention relates generally to the fabrication of semiconductor devices, and particularly to an advanced barrier film useful for forming single crystal metal in electronic devices.
Integrated circuits (ICs) are composed of vast number of active components such as transistors, resistors, and capacitors, and other active devices. These individual components are generally laid out in a two dimensional array on a substrate, such as silicon or gallium arsenide. The two dimensional arrays are often stacked on top of one another to form a three dimensional IC. As in any circuit, these components, and the several layers, must be connected to one another electrically. Interconnection on the two dimensional surfaces is accomplished by depositing lines or strips of metal that act as connecting “wires”. Likewise, different levels of the metallization are interconnected vertically by metal plugs deposited in via holes made between the separate layers (levels). These steps in the manufacturing process are commonly referred to as “metallization”, and are generally done as part of back-end-of-the-line processing.
Generally, silicon is the substrate material of choice, aluminum is the metal of choice for two dimensional IC metallization, and tungsten is the metal of choice for filling via holes for multiple layer interconnection. Silicon is preferred because it is cheap and abundant. Aluminum and tungsten are chosen because they have adequate electrical conductivity and they can be made not to diffuse into the substrate during the many annealing operations inherent in the IC manufacturing process.
However, because the electrical conductivity of aluminum and tungsten is limited, the lines and plugs must be made thick enough to ensure minimal resistance to electric current between components and between levels. The relative large size of these conductors has become an issue for IC designers and fabricators interested in placing a greater density of circuit elements on an IC. In order to achieve greater performance from ICs, the lateral dimensions of the circuit elements must be reduced. This reduction in IC element size has two detrimental effects on the resulting IC. First, it increases the resistance of the metal interconnects. Second, it increases the aspect ratio of the via holes, making them more difficult to fill with the metallic material. Incomplete filling of the via holes exacerbates the problem of high resistance. Today, there is often not enough space in the lateral direction on an IC chip to accommodate large aluminum conductors. Additionally, the size of the via holes, when filled with tungsten, limits the number of levels in the IC.
Copper has attracted widespread interest in the semiconductor processing field as an alternative metallization material. Because of copper's greater electrical conductivity, copper conductors impose less resistance to the flow of electrons than aluminum or tungsten conductors having equivalent dimensions. In principle, smaller conductor lines should be feasible with copper to carry the same amount of current as aluminum or tungsten. Thus, the goal has been to achieve a tighter packing density per level, or reduce the number of metallization levels, using a copper interconnect strategy. Also, copper has superior resistance to poisoning due to electromigration from adjoining layers than aluminum, which also should make it a more reliable conductor. Therefore, copper has represented an attractive candidate for back-end-of-the line metallization, among other things.
However, a practical copper interconnect strategy for semiconductor devices has faced several problems. For instance, copper is susceptible to corrosion because it does not form a native self protective oxide surface film. Also, the electrochemical activity of copper is conducive to corrosion. As a consequence, adequate precautions are needed to protect the copper surface during polishing, cleaning and post-processing operations. However, as an even more notable problem of current interest, copper has a tendency to diffuse relatively easily at elevated temperatures into silicon. The copper which migrates into the silicon tends to produce deep-level defects, which can severely degrade the electrical characteristics of the devices. The probability of this problem arising is heightened due to the fact that ICs must be annealed several times during the fabrication process.
As efforts to impede the diffusion of copper into silicon and other adjacent materials, a variety of materials has already been proposed and used to form diffusion barriers and/or encapsulants for copper conductors. Previous copper barriers are described, for instance, in U.S. Pat. Nos. 5,151,168 (Gilton et al.), 5,695,810 (Dubin et al.), and 5,824,599 (Schacham-Diamand et al.). Currently, a special need exists for suitable barrier films for copper-filled damascene lines. That is, as known, copper is relatively difficult to etch so its implementation in interconnect schemes generally requires additive patterning, such as damascene patterning, in lieu of subtractive processing.
Among the barrier materials under development within the semiconductor industry, nitrides or silico-nitrides of the transition metals titanium, tantalum and tungsten (e.g., TiN, TaN, WN, TiWN, TiSiN, and TaSiN) are prevalently used. The thickness of the metal-nitride barrier layer required to stop copper diffusion into silicon effectively is in the range of tens to hundreds of nanometers, or hundreds to thousands of Angstroms (Å). As shown in FIG. 2, which is based on published Semniconductor Industry Association data, presently achievable effective diffusion barrier thicknesses are generally in the 200-250 Å range for tantalum nitride, for example, although barrier film thicknesses for metallic copper that are smaller than that have been suggested in the prior art (e.g., see U.S. Pat. 5,824,599 to Schacham-Diamand et al.). A thick barrier layer can frustrate the advantage of using copper interconnects. Therefore, very thin barrier layers for copper are needed which still can maintain barrier efficacy even as the circuit feature sizes inexorably continue to shrink.
Another practical problem associated with implementing copper interconnects arises from the present state-of-the art wafer technology. Wafers for processing, ideally, would be atomically smooth, or equivalently have a perfect two-dimensional surface. This requirement typically is not completely met, i.e., it is not generally satisfied for the entire surface area of a standard 3 inch (7.6 cm) silicon wafer. In practice, microscopic steps and terraces of height more than one atomic layer usually exist and occur on any wafer that is manufactured from bulk crystals. In addition, the crystal orientation of the wafer generally is not perfect, as consequently there will be mis-oriented grains and grain boundaries that extend to the surface of the wafer. These imperfections on the wafer will tend to undermine conventional atomic diffusion barriers as they provide pathways for the diffusion of the copper atoms.
The problem of diffusion exists not only in the case of copper metallization on silicon, but also in the case of copper metallization on other single- and polycrystalline semiconductor substrate materials such as gallium arsenide, silicon carbide, germanium, and so forth. Also, copper diffusion or drift into insulating or dielectric materials, such as SiO2, can result in short circuits, especially in dense arrays of IC components. Diffusion is also a problem with other high conductivity metallization materials such as gold, silver, and platinum.
As can be appreciated from the foregoing, a barrier film is needed which is extremely thin, yet permits metallization using copper and other high conductivity metallic conductors which would otherwise have a tendency to diffuse into a substrate formed of a semiconducting material or an insulating material. It is further desired to improve electronic and electro-optic devices by making it possible to achieve one or more of the following desirable characteristics: increased component density in large scale integration, reduced heat dissipation, increased speed of operation, and a decreased number of metallization levels.